ASIC Timing & Power Engineer

Untether in Toronto

***Please note: While our engineering HQ is in Toronto, this is a remote opportunity and we welcome applicants from anywhere in North America.***

We are looking for a physical backend engineer with experience in DC-Shell, Primetime, and Primepower.
About Untether AI:

Untether AI is developing a groundbreaking new architecture that will bring neural net inference to new levels of performance and efficiency. Founded in Toronto in 2018 by a team of scientists and entrepreneurs, Untether AI’s ultra-efficient, high performance AI chips will eliminate the data movement bottleneck that costs energy and performance in traditional architectures. With the support of tier one investors, we are challenging the status quo with an architecture that is fundamentally unique. Working with us means getting the opportunity to be a part of something big - a chance to create the future of AI.
    • 7+ years in in RTL design (Verilog/SystemVerilog)
    • Experience in Primetime, Primepower, DC-shell, DC compiler, STA, Timing Closure (including Timing Closure using Primetime), CDC analysis, VCS, Low power design
    • Experience with Dynamic power analysis and design using VCD files and DC-shell/Power compiler/Primepower
    • Experience with Linux, Make, and Bash
    • Experience with Tcl
    • Good verbal and written communication skills
    • Ability to work independently and as part of a team
    • Problem-solving and trouble-shooting skills; ability to take initiative and solve problems
    • High performance IP RTL design with low power design techniques .
    • Focus on timing (writing constraints), STA, LINT and CDC closure to ensure high quality RTL, power analysis
    • Writing testbenches, simulation
    • Good understanding PCI Express and Computer Architecture.
    • Knowledge of memory interfaces (DDR/LPDDR/etc.)
    • Working experience in Python/C/C++/Assembly
    • Working experience in verification with UVM.
    • Able to cross check between Primetime and Spice simulations
    • Team Lead experience
    • Experience with Spyglass (LINT, CDC)
    • Experience with Verilog Coding
    • Knowledge of UPF flow for defining power intent of chips with multiple power domains
Apply