The Tenstorrent team combines technologists from different disciplines who come together with a shared passion for AI and a deep desire to build great products. We value collaboration, curiosity, and a commitment to solving hard problems. Find out more about our culture .

CPU Microarchitecture/RTL engineer focusing on MidCore block for high-performance CPUs. The person coming into this role will work with a highly experienced team and deliver a functional, timing and power converged block.

Multiple geographies: Austin, Santa Clara

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

RTL design and Microarchitecture of the Mid Core unit for a from-scratch high performance CPU based on RISCV ISA, working closely with the DV and PD team
RTL coding in Verilog leveraging on both industry tools as well as open-source infrastructure
Work with design, test and post silicon validation teams for high quality delivery of the MidCore block
Drive trade-offs for your logic by working closely with performance, DV and physical design engineers to craft optimal solutions that meet the design goals
Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results
Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environment
Enhance RTL design environment, tools and infrastructure

BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
Strong background and experience with high performance OOO CPU microarchitecture
Experience working on an x86, ARM or RISCV based CPU
Architectural understanding of Rename, Scheduler, Reorder Buffer and Datapath for an Out of Order CPU
Expertise in logic design and ability to evaluate functional, performance, timing and power for you design
Strong experience with hardware description languages (Verilog, VHDL), simulators (VCS, NC, Verilator), Synthesis and Power tools
Expertise in microarchitecture definition and specification development
Strong problem solving and debug skills across various levels of design hierarchies

Apply

CPU MidCore RTL/Microarchitecture Engineer

Tenstorrent in Austin, TX