Lead CPU Load/Store Verification Engineer

Tenstorrent in Bangalore, Karnataka

The Tenstorrent team combines technologists from different disciplines who come together with a shared passion for AI and a deep desire to build great products. We value collaboration, curiosity, and a commitment to solving hard problems. Find out more about our culture .

Technical lead focused on Load Store verification for high-performance CPUs. The person coming into this role will help define the overall load store verification strategy, lead the DV plan and execution for this domain.


Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
    • Lead functional and performance verification of the load store unit for a from-scratch high performance CPU while working closely with Architecture and RTL team
    • Develop detailed block level verification plans for load store that includes both architectural (RISCV ISA) and microarchitectural functionality
    • Design and develop reusable block level testbench components in SV, UVM and C++, that include microarchitectural models, monitors, checkers
    • Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
    • Evaluate and integrate open-source toolchains into the DV flow
    • Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
    • Work with design, test and post silicon validation teams to ensure high quality delivery of the load store block
    • BS/MS/PhD in EE/ECE/CE/CS with at least 8 years of experience
    • Strong background and experience with high performance OOO CPU microarchitecture especially with load/store, caches and memory subsystem
    • Experience working on an x86, ARM or RISCV based CPU
    • Architectural understanding of address translation, memory ordering, cache coherence protocols, memory consistency and multi-processors
    • Significant experience debugging RTL and DV in a simulation environment
    • Verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
    • Experience with C++ / SV / UVM as well as scripting languages
    • Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
    • Strong problem solving and debug skills across various levels of design hierarchies
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