Lead Debug and Trace Design Verification Engineer

Tenstorrent in Bangalore, Karnataka

The Tenstorrent team combines technologists from different disciplines who come together with a shared passion for AI and a deep desire to build great products. We value collaboration, curiosity, and a commitment to solving hard problems. Find out more about our culture .

Verification architect focused on Debug and Trace Logic for high-performance CPUs. The person coming into this role will help define the overall design for debug strategy, lead the DV plan and execution for this domain.
Location:

We have presence in Toronto (CAN), Austin, Santa Clara, Portland, Boston, and Raleigh (US), as well as Bangalore (India), and Cambridge (UK). We are open to remote candidates on a case by case basis.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
    • Define design for Debug requirements for a from-scratch high performance CPU working closely with Architecture and RTL team
    • Develop detailed verification plans for debug and trace logic for a server class CPU based on RISCV ISA
    • Design and develop component, block and core level testbenches including stimulus engines, microarchitectural models, checkers
    • Develop stimulus that spans pre-silicon, emulation and post-silicon domain
    • Evaluate and integrate open-source toolchains into the DV flow
    • Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
    • Work with design, test and post silicon validation teams to deploy debug features
    • BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
    • Experience with Debug, Trace, JTAG and other design for debug (DFD) domains for an x86, ARM or RISCV based CPU
    • Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
    • Verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
    • Experience with C++ / SV / UVM as well as scripting languages
    • Experience with assembly level programming
    • Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
    • Strong problem solving and debug skills across various levels of design hierarchies RISCV, Debug and Trace Verification Engineer
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