Lead Package Design Engineer

Tenstorrent in Santa Clara, CA

The person hired for this role will lead package design for high-performance chiplets and SOCs. They will be involved in all stages, from concept to high-volume manufacturing, and will be responsible for designing packaging solutions that meet industry leading power, performance, and cost targets.  The work will be done alongside a group of highly experienced engineers across various domains of the AI/ML chip.
Locations:
Austin, TX | Santa Clara, CA

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
    • All aspects of package design including SI/PI, STA, routing, reliability, thermal, mechanical, manufacturability, bumping, substrate, material selection, assembly, and support for testing
    • All aspects of package planning including pre/post silicon bring up, yield improvements, qualification, failure analysis, and system implementation
    • Collaborating with design engineers to develop a portfolio of chiplets that meets a huge range of price-performance design points while optimizing re-use
    • Meeting specifications for high speed interfaces such as HBM, DDR, GDDR, PCIE, 112G SerDes
    • Overseeing OSAT and substrate suppliers
    • Managing the production of the IC package, including monitoring the manufacturing process and ensuring that the package is produced to the required quality and reliability standards
    • BS/MS/PhD in EE/ECE/ME/ChemE or related disciplines
    • More than 10 years of experience in advanced packaging design and implementation
    • Hands-on experience with modeling thermo-mechanical stress and/or SI/PI
    • Well versed in advanced packaging techniques including InFO, CoWoS, FoCoS, EMIB variants, hybrid bonding
    • Excellent understanding of circuit, mechanical, and thermodynamic fundamentals
    • Experience with optical module integration is an asset
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