Physical Design Engineer
Tenstorrent in Santa Clara, CA
The role is physical design for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.
Locations:
Austin, TX | Santa Clara, CA
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
- Work closely with other PD engineers and the front end team to understand the chip architecture and drive physical design considerations early in the project cycle
- Physical design tasks such as synthesis, PnR, timing closure, area improvement, floor-planning, clocking, I/O planning and power optimization
- Learn and implement end-to-end flow development, synthesis to sign off
- Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results
- BS/MS/PhD in EE/ECE/CE/CS
- Some experience with synthesis, place and route flows and tools
- Basic familiarity with timing, EM/IR, and power analysis tools
- Knowledge of low-power design techniques such as power gating, multi-Vt and voltage scaling
- Strong programming skills in Tcl/Perl/Shell/Python
- Good understanding of logic design fundamentals and gate/transistor level implementation
- Strong problem-solving skills