Senior ASIC Digital Design Verification Engineer

Untether in Canada

***Please note: While our engineering HQ is in Toronto, this is a remote opportunity and we welcome applicants from anywhere in North America.***

We are looking for a RTL and gatelevel verification engineer with experience in UVM, VCS, Python.
About Untether AI:

Untether AI is developing a groundbreaking new architecture that will bring neural net inference to new levels of performance and efficiency. Founded in Toronto in 2018 by a team of scientists and entrepreneurs, Untether AI’s ultra-efficient, high performance AI chips will eliminate the data movement bottleneck that costs energy and performance in traditional architectures. With the support of tier one investors, we are challenging the status quo with an architecture that is fundamentally unique. Working with us means getting the opportunity to be a part of something big - a chance to create the future of AI.
    • 10+ years in in RTL design (Verilog/SystemVerilog)
    • Experience in UVM, VCS, Python, Low power design
    • Writing test benches, simulation
    • High performance IP RTL design with low power design techniques
    • Good understanding of PCI Express
    • Good verbal and written communication skills
    • Ability to work independently and as part of a team
    • Problem-solving and trouble-shooting skills; ability to take initiative and solve problems

    • Good understanding of computer architecture
    • Knowledge of memory interfaces (DDR/LPDDR/etc.)
    • Working knowledge of Linux
    • Working experience in Python/C/C++/Assembly
    • Working experience in verification with UVM.
    • Team Lead experience
    • Experience with Spyglass (LINT, CDC)
    • Experience with Verilog Coding
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