Sr. Design for Test Engineer

Tenstorrent in Austin, TX

The Tenstorrent team combines technologists from different disciplines who come together with a shared passion for AI and a deep desire to build great products. We value collaboration, curiosity, and a commitment to solving hard problems. Find out more about our culture .

Position is Design for Test and Design for Debug (DFT/DFD or DFx) engineer for high-performance designs going into industry leading AI/ML architecture. The person coming into this role will be involved in all aspects of implementation and verification of advanced DFx techniques for various IPs. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done alongside with a group of highly experienced engineers across various domains of the AI ASIC.
Locations:
Austin, TX | Santa Clara, CA | Fort Collins, CO

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency information and/or documentation will be required and considered as Tenstorrent moves through the employment process.
    • ATPG and test coverage analysis using industry standard tools.
    • JTAG, Scan Compression, and ASST implementation.
    • Gate level simulation using Synopsys VCS and Verdi.
    • Support silicon bring-up and debug.
    • MBIST planning, implementation, and verification.
    • Support Test Engineering on planning, patterns, and debug.
    • Develop efficient DFx flows and methodology compatible with front end and physical design flows.
    • BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques.
    • DFx experience implementing in finFET technologies.
    • Experience with industry standard ATPG and DFx insertion CAD tools.
    • Familiarity with SystemVerilog and UVM.
    • Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
    • Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
    • Good understanding of high-performance, low-power design fundamentals.
    • Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
    • Exposure to post-silicon testing and tester pattern debug are major assets.
    • Experience with Fault Campaigns a plus.
    • Strong problem solving and debug skills across various levels of design hierarchies.
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