Sr. Physical Design Flow Engineer, AI Silicon

Tenstorrent in Santa Clara, CA

Develop physical design flow for high-performance designs going into industry leading AI/ML architecture. The person coming into this role will be involved in all aspects of optimizing flows from synthesis to tape-out for various IPs on the chip. The work is done alongside a group of highly experienced engineers across various domains of the AI chip.
Locations:
Austin, TX or Santa Clara, CA

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
    • Work closely with physical design team and tool vendors to define flow requirements
    • Flow tasks may include enabling targets such as floor-planning, synthesis, PnR, timing and phy closure
    • Optimize and support PnR flow to ensure quality results on schedule
    • Discussions with vendor tool providers, foundry partners and design services
    • End to end tasks from flow development to sign-off
    • Deploy innovative techniques for improving power, performance and area of the design, drive experiments with PD, and evaluate PnR, timing and power results
    • BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience
    • Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
    • Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
    • Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc.
    • Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
    • Strong programming skills in Tcl/Perl/Shell/Python
    • Excellent understanding of logic design fundamentals and gate/transistor level implementation
    • Exposure to DFT is an asset
    • Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
    • Strong problem solving and debug skills across various levels of design hierarchies
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